In recent years, all digital phase locked loop (ADPLL) circuits where all control signals of phase locked loop (PLL) circuits are digitized are used in wireless communication devices such as wireless LAN devices (for example, see Japanese Patent Application Publication (KOKAI) No. 2009-21954). Since analog circuits are replaced by digital circuits in ADPLL circuits, it is possible to save space and power due to progress in processes.
An ADPLL circuit includes a digital loop filter, a digitally-controlled oscillator (DCO), a counter and a time-to-digital converter (TDC). The counter counts an output CKV of the DCO and outputs a count value based on a reference signal synchronized with the outputs CKV of the DCO. The TDC obtains a phase difference of one cycle or less of an output CKV of the DCO in synchronization with the reference signal REF. A comparison result (difference) between a value obtained by adding the count value to the phase difference d and a phase control signal is supplied to the digital loop filter. The oscillation frequency of the DCO is controlled based on the output of the digital loop filter.
The output CKV of the DCO and the reference signal REF are asynchronous. That is, in the ADPLL circuit, the respective outputs from the two circuits (the counter and the TDC) that operate with asynchronous clocks are added in the same circuit. Thus, the read value of the counter may be shifted, which causes unstable PLL operation.
In particular, disadvantages lie in that (1) the circuit for obtaining phase information from the output CKV of the DCO is constituted by two circuits (the counter and the TDC) having different functions and that (2) the output of the counter is the reference signal REF synchronized with the output CKV of the DCO.